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? 2002-2012 microchip technology inc. ds21703l-page 1 24aa16/24lc16b device selection table features: single supply with operation down to 1.7v for 24aa16 devices, 2.5v for 24lc16b devices low-power cmos technology: - active current 1 ma, typical - standby current, 1 ? a, typical 2-wire serial interface, i 2 c? compatible schmitt trigger inputs for noise suppression output slope control to eliminate ground bounce 100 khz and 400 khz clock compatibility page write time 5 ms max. self-timed erase/write cycle 16-byte page write buffer hardware write-protect esd protection > 4,000v more than 1 million erase/write cycles data retention > 200 years factory programming available packages include 8-lead pdip, soic, tssop, msop, dfn, tdfn, 5-lead sot-23 and chip scale pb-free and rohs compliant temperature ranges: - industrial (i): -40c to +85c - automotive (e): -40c to +125c description: the microchip technology inc. 24aa16/24lc16b (24xx16*) is a 16 kbit electrically erasable prom. the device is organized as eight blocks of 256 x 8-bit memory with a 2-wire serial interface. low-voltage design permits operation down to 1.7v with standby and active currents of only 1 ? a and 1 ma, respectively. the 24xx16 also has a page write capability for up to 16 bytes of data. the 24xx16 is available in the standard 8-pin pdip, surface mount soic, tssop, 2x3 dfn, 2x3 tdfn and msop pack- ages, and is also available in the 5-lead sot-23, and chip scale packages. block diagram part number v cc range max. clock frequency temp. ranges 24aa16 1.7-5.5 400 khz (1) i, e 24lc16b 2.5-5.5 400 khz i, e note 1: 100 khz for v cc <2.5v. hv eeprom array page ydec xdec sense amp. memory control logic i/o control logic i/o wp sda scl v cc v ss r/w control latches generator a0a1 a2 v ss v cc wp scl sda 12 3 4 87 6 5 pdip/msop/soic/tssop dfn/tdfn a0 a1 a2 v ss wp sclsda v cc 87 6 5 1 2 3 4 sot-23 1 2 34 5 wp v cc scl v ss sda note 1: pins a0, a1 and a2 are not used by the 24xx16 (no internal connections). 2: available in i-temp, aa only. cs (chip scale) (1) 1 2 3 45 v cc wp sda scl v ss (top down view, balls not visible) 16k i 2 c? serial eeprom *24xx16 is used in this document as a generic part number for the 24aa16/24lc16b devices. downloaded from: http:///
24aa16/24lc16b ds21703l-page 2 ? 2002-2012 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.3v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c esd protection on all pins ???????????????????????????????????????????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 4kv table 1-1: dc characteristics ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating condition s for extended periods may affect device reliability. dc characteristics industrial (i): t a = -40c to +85c, v cc = +1.7v to +5.5v automotive (e): t a = -40c to +125c, v cc = +1.7v to +5.5v param. no. symbol characteristic min. typ. max. units conditions wp, scl and sda pins d1 v ih high-level input voltage 0.7 v cc v d2 v il low-level input voltage 0.3 v cc v d3 v hys hysteresis of schmitt trigger inputs 0.05 v cc v ( note 1 ) d4 v ol low-level output voltage 0.40 v i ol = 3.0 ma, v cc = 2.5v d5 i li input leakage current 1 ? av in = v ss or v cc d6 i lo output leakage current 1 ? av out = v ss or v cc d7 c in , c out pin capacitance (all inputs/outputs) 1 0p f v cc = 5.0v ( note 1 ) t a = 25c, f clk = 1 mhz d8 i cc write operating current 3m a v cc = 5.5v, scl = 400 khz d9 i cc read 0.01 1 ma d10 i ccs standby current 0.3 0.01 15 ? a ? a industrial automotive sda = scl = v cc wp = v ss note 1: this parameter is periodically sampled and not 100% tested. 2: typical measurements taken at room temperature. downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 3 24aa16/24lc16b table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c, v cc = +1.7v to +5.5v automotive (e): t a = -40c to +125c, v cc = +1.7v to +5.5v param. no. symbol characteristic min. max. units conditions 1f clk clock frequency 400 100 khz 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 2 t high clock high time 600 4000 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 3t low clock low time 1300 4700 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 4t r sda and scl rise time ( note 1 ) 300 1000 ns 2.5v ? v cc ? 5.5v ( note 1 ) 1.7v ? v cc ? 2.5v (24aa16) ( note 1 ) 5t f sda and scl fall time 300 ns ( note 1 ) 6t hd : sta start condition hold time 600 4000 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 7t su : sta start condition setup time 600 4700 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 8t hd : dat data input hold time 0 ns ( note 2 ) 9t su : dat data input setup time 100 250 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 10 t su : sto stop condition setup time 600 4000 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 11 t aa output valid from clock ( note 2 ) 900 3500 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 12 t buf bus free time: time the bus must be free before a new transmission can start 1300 4700 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 13 t of output fall time from v ih minimum to v il maximum 20+0.1c b 250 250 ns 2.5v ? v cc ? 5.5v 1.7v ? v cc ? 2.5v (24aa16) 14 t sp input filter spike suppression (sda and scl pins) 5 0n s ( notes 1 and 3 ) 15 t wc write cycle time (byte or page) 5m s 16 endurance 1m cycles 25c, ( note 4 ) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endu rance estimates in a specific application, please consult the total endurance? mo del which can be obtained from microchips web site at www.microchip.com. downloaded from: http:///
24aa16/24lc16b ds21703l-page 4 ? 2002-2012 microchip technology inc. figure 1-1: bus timing data figure 1-2: bus timing start/stop 7 5 2 4 8 9 10 12 11 14 6 scl sda in sda out 3 7 6 d3 10 start stop scl sda downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 5 24aa16/24lc16b 2.0 pin descriptions the descriptions of the pins are listed in tab l e 2 - 1 . table 2-1: pin function table 2.1 serial address/data input/output (sda) sda is a bidirectional pin used to transfer addresses and data into and out of the device. since it is an open- drain terminal, the sda bus requires a pull-up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating start and stop conditions. 2.2 serial clock (scl) the scl input is used to synchronize the data transfer to and from the device. 2.3 write-protect (wp) the wp pin must be connected to either v ss or v cc . if tied to v ss , normal memory operation is enabled (read/write the entire memory 000-7ff). if tied to v cc , write operations are inhibited. the entire memory will be write-protected. read operations are not affected. 2.4 a0, a1, a2 the a0, a1 and a2 pins are not used by the 24xx16. they may be left floating or tied to either v ss or v cc . name pdip soic tssop dfn tdfn msop sot-23 cs description a0 1 1 1 1 1 1 not connected a1 2 2 2 2 2 2 not connected a2 3 3 3 3 3 3 not connected v ss 4 4 4 4 4 4 2 2 ground sda 5 5 5 5 5 5 3 5 serial address/data i/o scl 6 6 6 6 6 6 1 4 serial clock wp 7 7 7 7 7 7 5 3 write-protect input v cc 8 8 8 8 8 8 4 1 +1.7v to 5.5v power supply downloaded from: http:///
24aa16/24lc16b ds21703l-page 6 ? 2002-2012 microchip technology inc. 3.0 functional description the 24xx16 supports a bidirectional, 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, while a device receiving data is defined as a receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions, while the 24xx16 works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined ( figure 4-1 ). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is determined by the master device and is, theoretically, unlimited (although only the last sixteen will be stored when doing a write operation). when an overwrite does occur it will replace data in a first-in first-out (fifo) fashion. 4.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges, has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable-low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xx16) will leave the data line high to enable the master to generate the stop condition. figure 4-1: data transfer sequence on the serial bus note: the 24xx16 does not generate any acknowledge bits if an internal programming cycle is in progress. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 7 24aa16/24lc16b 5.0 device addressing a control byte is the first byte received following the start condition from the master device ( figure 5-1 ). the control byte consists of a four-bit control code. for the 24xx16, this is set as 1010 binary for read and write operations. the next three bits of the control byte are the block-select bits (b2, b1, b0). they are used by the master device to select which of the eight 256 word-blocks of memory are to be accessed. these bits are in effect the three most significant bits (msb) of the word address. it should be noted that the protocol limits the size of the memory to eight blocks of 256 words, therefore, the protocol can support only one 24xx16 per system. the last bit of the control byte defines the operation to be performed. when set to 1 , a read operation is selected. when set to 0 , a write operation is selected. following the start condition, the 24xx16 monitors the sda bus, checking the device type identifier being transmitted and, upon receiving a 1010 code, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24xx16 will select a read or write operation. figure 5-1: control byte allocation figure 5-2: address sequence bit assignments operation control code block select r/w read 1010 block address 1 write 1010 block address 0 10 10 b2 b1 b0 r/w ack start bit read/write bit s slave address acknowledge bit control code block select bits 1010 b 2 b 1 b 0 r/w a 7 a 0 control byte address low byte control code block select bits downloaded from: http:///
24aa16/24lc16b ds21703l-page 8 ? 2002-2012 microchip technology inc. 6.0 write operation 6.1 byte write following the start condition from the master, the device code (4 bits), the block address (3 bits) and the r/w bit, which is a logic-low, is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow once it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmit- ted by the master is the word address and will be written into the address pointer of the 24xx16. after receiving another acknowledge signal from the 24xx16, the master device will transmit the data word to be written into the addressed memory location. the 24xx16 acknowledges again and the master generates a stop condition. this initiates the internal write cycle and, during this time, the 24xx16 will not generate acknowledge signals ( figure 6-1 ). 6.2 page write the write control byte, word address and the first data byte are transmitted to the 24xx16 in the same way as in a byte write. however, instead of generating a stop condition, the master transmits up to 16 data bytes to the 24xx16, which are temporarily stored in the on- chip page buffer and will be written into memory once the master has transmitted a stop condition. upon receipt of each word, the four lower-order address pointer bits are internally incremented by 1 . the higher-order 7 bits of the word address remain constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an internal write cycle will begin ( figure 6-2 ). 6.3 write protection the wp pin allows the user to write-protect the entire array (000-7ff) when the pin is tied to v cc . if tied to v ss the write protection is disabled. figure 6-1: byte write note: page write operations are limited to writ- ing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page-size) and end at addresses that are integer multiples of [page size C 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. s p bus activity master sda line bus activity st a r t st o p control byte word address data ac k ac k ac k 10 1 0 b2 b1 b0 0 block select bits downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 9 24aa16/24lc16b figure 6-2: page write s p bus activity master sda line bus activity st a r t control byte word address ( n) data (n) data (n + 15) st o p ac k ac k ac k ac k ac k data (n + 1) b1 b2 b0 1 0 1 0 0 block select bits downloaded from: http:///
24aa16/24lc16b ds21703l-page 10 ? 2002-2012 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally-timed write cycle and ack polling can then be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, no ack will be returned. if the cycle is complete, the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for a flow diagram of this operation. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 11 24aa16/24lc16b 8.0 read operation read operations are initiated in the same way as write operations, with the exception that the r/w bit of the slave address is set to 1 . there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24xx16 contains an address counter that main- tains the address of the last word accessed, internally incremented by 1 . therefore, if the previous access (either a read or write operation) was to address n , the next current address read operation would access data from address n + 1 . upon receipt of the slave address with r/w bit set to 1 , the 24xx16 issues an acknowl- edge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24xx16 discontinues transmission ( figure 8-1 ). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is accomplished by sending the word address to the 24xx16 as part of a write operation. once the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the inter- nal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a 1 . the 24xx16 will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24xx16 will discontinue transmission ( figure 8-2 ). 8.3 sequential read sequential reads are initiated in the same way as a random read, except that once the 24xx16 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24xx16 to transmit the next sequentially- addressed 8-bit word ( figure 8-3 ). to provide sequential reads, the 24xx16 contains an internal address pointer that is incremented by one upon completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 8.4 noise protection the 24xx16 employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5v at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. figure 8-1: current address read sp bus activity master sda line bus activity st o p control byte data (n) ac k no a c k st a r t 1 0 10 1 b2 b1 b0 block select bits downloaded from: http:///
24aa16/24lc16b ds21703l-page 12 ? 2002-2012 microchip technology inc. figure 8-2: random read figure 8-3: sequential read s p s bus activity master sda line bus activity st a r t st o p control byte ac k word address (n) control byte st a r t data (n) ac k ac k n o a c k 10 10 0 b2b1 b0 11 0 0 1 b2 b1b0 block select bits block select bits p bus activity master sda line bus activity st o p control byte ac k n o a c k data (n) data (n + 1) data (n + 2) data (n + x ) ac k ac k ac k 1 downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 13 24aa16/24lc16b 9.0 packaging information 9.1 package marking information xxxxxxxxt/xxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (3.90 mm) example: xxxxxxxt xxxxyyww nnn 8-lead tssop example: 24lc16b i/p 13f 0527 24lc16bi sn 0527 13f 8-lead msop example: xxxx tyww nnn xxxxxt ywwnnn 4l16 i527 13f 4l16i 52713f 5-lead sot-23 example: xxnn b53f 8-lead 2x3 dfn example: 254527 13 xxx yww nn 3 e 3 e 8-lead 2x3 tdfn example: a54 527 13 xxx yww nn downloaded from: http:///
24aa16/24lc16b ds21703l-page 14 ? 2002-2012 microchip technology inc. part number 1st line marking codes tssop msop sot-23 dfn tdfn i temp. e temp. i temp. e temp. i temp. e temp. 24aa16 4a16 4a16t b5nn 7vnn 251 a51 ee9 24lc16b 4l16 4l16t m5nn n5nn 254 255 a54 a55 note: t = temperature grade (i, e) nn = alphanumeric traceability code 5-lead chip scale xw example: 57 legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e note: please visit www.microchip.com/pbfree for the latest information on pb-free conversion. * standard otp marking consists of microchip part number, year code, week code, and traceabili ty code. downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 15 24aa16/24lc16b n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c downloaded from: http:///
24aa16/24lc16b ds21703l-page 16 ? 2002-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 17 24aa16/24lc16b note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa16/24lc16b ds21703l-page 18 ? 2002-2012 microchip technology inc. downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 19 24aa16/24lc16b d n e e1 note 1 12 b e c a a1 a2 l1 l downloaded from: http:///
24aa16/24lc16b ds21703l-page 20 ? 2002-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 21 24aa16/24lc16b d n e note 1 1 2 exposed pad note 1 2 1 d2 k l e2 n e b a3 a1 a note 2 bottom view top view downloaded from: http:///
24aa16/24lc16b ds21703l-page 22 ? 2002-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 23 24aa16/24lc16b note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa16/24lc16b ds21703l-page 24 ? 2002-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 25 24aa16/24lc16b downloaded from: http:///
24aa16/24lc16b ds21703l-page 26 ? 2002-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 27 24aa16/24lc16b note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa16/24lc16b ds21703l-page 28 ? 2002-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 29 24aa16/24lc16b n b e e1 d 1 2 3 e e1 a a1 a2 c l l1 downloaded from: http:///
24aa16/24lc16b ds21703l-page 30 ? 2002-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 31 24aa16/24lc16b note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa16/24lc16b ds21703l-page 32 ? 2002-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging please contact your local microchip representative for specific details. downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 33 24aa16/24lc16b note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa16/24lc16b ds21703l-page 34 ? 2002-2012 microchip technology inc. appendix a: revision history revision d (12/2003) corrections to section 1.0, electrical characteristics. revision e (3/2005) added dfn package. revision f (9/2005) revised figure 3-2 control byte allocation; figure 4-1 byte write; figure 4-2 page write; section 6.0 write protection; figure 7-1 current address read; figure 7- 2 random read; figure 7-3 sequential read; section 8.3 write-protect (wp). revision g (02/2007) changed 1.8v to 1.7v; revised features section; replaced package drawings; revised product id section. revision h (01/2009) added tdfn package; updated package drawings. revision j (10/2009) added 5-lead chip scale package. revision k (01/2012) added chip scale package; revised product id system. revision l (12/2012) revised automotive e-temp.; product id system. downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 35 24aa16/24lc16b the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
24aa16/24lc16b ds21703l-page 36 ? 2002-2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in whic h our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21703l 24aa16/24lc16b 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 37 24aa16/24lc16b product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package temperature range device 24aa16: = 1.7v, 16 kbit i 2 c serial eeprom 24aa16t: = 1.7v, 16 kbit i 2 c serial eeprom (tape and reel) 24lc16b: = 2.5v, 16 kbit i 2 c serial eeprom 24lc16bt: = 2.5v, 16 kbit i 2 c serial eeprom (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (3.90 mm body), 8-lead st = plastic tssop (4.4 mm), 8-lead ms = plastic micro small outline (msop), 8-lead ot = plastic sot-23, 5-lead (tape and reel only) mc = plastic dfn (2x3x0.90 mm body), 8-lead mny (1) = plastic tdfn, (2x3x0.75 mm body), 8-lead cs16k (2) = chip scale (cs), 5-lead (i-temp, aa tape and reel only) note 1: y indicates a nickel palladium gold (nipdau) finish. 2: 16k indicates 160k technology. examples: a) 24aa16-i/p: industrial temperature,1.7v, pdip package b) 24aa16-i/sn: industrial temperature,1.7v, soic package c) 24aa16t-i/ot: industrial temperature, 1.7v, sot-23 package, tape and reel d) 24aa16t-i/cs16k: industrial temperature, 1.7v, chip scale package, tape and reel e) 24lc16b-i/p: industrial temperature, 2.5v, pdip package f) 24lc16b-e/sn: automotive temp.,2.5v soic package g) 24lc16bt-i/ot: industrial temperature, 2.5v, sot-23 package, tape and reel h) 24aa16t-e/sn: automotive temperature, 1.7v, soic package, tape and reel downloaded from: http:///
24aa16/24lc16b ds21703l-page 38 ? 2002-2012 microchip technology inc. notes: downloaded from: http:///
? 2002-2012 microchip technology inc. ds21703l-page 39 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2002-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620767634 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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